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| ST10F163 16-BIT MCU WITH 128KBYTE FLASH MEMORY s s s PEC Interrupt Controller s P.4 P.1 P.0 PLL GPT1&2 EBC s s SSP BRG BRG ASC P.6 P.5 P.3 P.2 April 1999 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Watchdog 1/58 s s HIGH PERFORMANCE CPU - HIGH PERFORMANCE 16-BIT CPU WITH 4-STAGE PIPELINE - 80ns INSTRUCTION CYCLE TIME @ 25MHz CPU CLOCK - 400ns MULTIPLICATION (16 x 16 BITS) - 800ns DIVISION (32 / 16 BIT) - ENHANCED BOOLEAN BIT MANIPULATION FACILITIES - ADDITIONAL INSTRUCTIONS TO SUPPORT HLL AND OPERATING SYSTEMS - SINGLE-CYCLE CONTEXT SWITCHING SUPPORT MEMORY ORGANIZATION - UP TO 16 MBYTES LINEAR ADDRESS SPACE FOR CODE AND DATA (1MBYTE WITH SSP USED) - 1 KBYTES ON-CHIP RAM - 128 KBYTES ON-CHIP FLASH MEMORY - 4 INDEPENDENTLY ERASABLE BANKS OF FLASH FAST AND FLEXIBLE BUS - PROGRAMMABLE EBC - 8-BIT OR 16-BIT EXTERNAL DATA BUS - MULTIPLEXED OR DEMULTIPLEXED EXTERNAL ADDRESS/DATA BUSES - FIVE PROGRAMMABLE CHIP-SELECT SIGNALS - HOLD AND HOLD-ACKNOWLEDGE BUS ARBITRATION SUPPORT ON-CHIP BOOTSTRAP LOADER FAIL-SAFE PROTECTION - PROGRAMMABLE WATCHDOG TIMER - OSCILLATOR WATCHDOG INTERRUPT - 8-CHANNEL INTERRUPT-DRIVEN SINGLE-CYCLE DATA TRANSFER FACILITIES VIA PERIPHERAL EVENT CONTROLLER (PEC) - 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH 20 SOURCES, SAMPLE-RATE DOWN TO 40ns TIMERS - TWO GENERAL PURPOSE TIMER UNITS WITH 5 TIMERS CLOCK GENERATION - ON-CHIP PLL - DIRECT OR PRESCALED CLOCK INPUT PQFP100 (14 x 14 mm) (Plastic Quad Flat Pack) s s s s s UP TO 77 GENERAL PURPOSE I/O LINES IDLE AND POWER DOWN MODES SERIAL CHANNELS - SYNCHRONOUS/ASYNCHRONOUS - HIGH-SPEEDSYNCHRONOUS SERIAL PORTSSP DEVELOPMENT SUPPORT - C-COMPILERS, MACRO-ASSEMBLER PACKAGES, EMULATORS, EVALUATION BOARDS, HLL-DEBUGGERS, SIMULATORS, LOGIC ANALYZER DISASSEMBLERS, PROGRAMMING BOARDS PACKAGE - 100-PIN THIN QUAD FLAT PACK (TQFP) FLASH CPU RAM ST10F163 TABLE OF CONTENTS I II III IV V V.1 V.1.1 V.1.2 V.2 V.3 VI VI.1 VII VIII IX IX.1 IX.2 X XI XII XIII XIV XV XVI XVI.1 XVI.2 XVI.3 XVI.4 XVI.4.1 XVI.4.2 XVI.4.3 XVI.4.4 XVI.4.5 XVI.4.6 INTRODUCTION ........................................................................................................ PIN DATA ............................................................................................................. Page 4 5 9 10 10 11 13 13 14 14 15 15 17 18 20 20 20 23 23 25 25 26 28 31 31 31 31 33 33 34 34 35 35 35 FUNCTIONAL DESCRIPTION ................................................................................... MEMORY ORGANIZATION ....................................................................................... FLASH MEMORY ...................................................................................................... PROGRAMMING/ERASING WITH ST EMBEDDED ALGORITHM KERNEL ............ Return values ............................................................................................................. Programming examples .............................................................................................. FLASH MEMORY CONFIGURATION......................................................................... FLASH PROTECTION ............................... ................................................................. EXTERNAL BUS CONTROLLER .............................................................................. PROGRAMMABLE CHIP SELECT TIMING CONTROL ............................................. CENTRAL PROCESSING UNIT (CPU) ..................................................................... INTERRUPT SYSTEM ............................................................................................... GENERAL PURPOSE TIMER (GPT) UNIT ........................................... .................... GPT1 ........................................................................................................................... GPT2 ........................................................................................................................... PARALLEL PORTS ............................................................................... .................... SERIAL CHANNELS ................................................................................................. WATCHDOG TIMER .................................................................................................. OSCILLATOR WATCHDOG (OWD) ......................................................................... INSTRUCTION SET SUMMARY ................................. .............................................. SPECIAL FUNCTION REGISTER OVERVIEW ......................................................... ELECTRICAL CHARACTERISTICS ........ ................................................................. ABSOLUTE MAXIMUM RATINGS ............. ................................................................. PARAMETER INTERPRETATION.............................................................................. DC CHARACTERISTICS ............................................................................................ AC CHARACTERISTICS............................................................................................. Test waveforms .......................................................................................................... Definition of internal timing ......................................................................................... Clock generation modes ............................................................................................. Prescaler operation .................................................................................................... Direct drive ................................................................................................................. Oscillator Watchdog (OWD) ................................................................... .................... 2/58 ST10F163 XVI.4.7 XVI.4.8 XVI.4.9 XVI.4.10 XVI.4.11 XVI.4.12 XVI.4.13 XVI.4.14 XVII XVIII XIX Phase locked loop ...................................................................................................... Memory cycle variables .............................................................................................. External clock drive XTAL1 .......................................... .............................................. Multiplexed bus ...................................................................................... .................... Demultiplexed bus ...................................................................................................... CLKOUT and READY ................................................................................................ External bus arbitration ........................................................................... .................... Synchronous serial port timing ................................................................................... PACKAGE MECHANICAL DATA ........................................................................... 35 36 37 38 44 50 52 54 56 56 57 ORDERING INFORMATION ...................................................................................... REVISION HISTORY ................................ ................................................................. 3/58 ST10F163 I - INTRODUCTION The ST10F163 is a Flash derivative of the STMicroelectronics ST10 family of 16-bit microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with Figure 1 : Logic symbol high peripheral functionality and enhanced IO-capabilities. 128KBytes of an electrically erasable and re-programmable Flash EPROM is provided on-chip. VDD XTAL1 XTAL2 RSTIN RSTOUT NMI EA READY ALE RD WR/WRL Port 5 6-bit VSS Port 0 16-bit Port 1 16-bit Port 2 8-bit Port 3 15-bit Port 4 8-bit Port 6 8-bit ST10F163 4/58 ST10F163 II - PIN DATA Figure 2 : TQFP pin configuration (top view) P5.12/T6IN P5.11/T5EUD P5.10/T6EUD P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/BREQ P6.6/HLDA P6.5/HOLD P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 NMI RSTOUT RSTIN VDD VSS P1H.7/A15 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P5.13/T5IN P5.14/T4EUD P5.15/T2EUD VSS XTAL1 XTAL2 VDD P3.0 P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8 P3.9 P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13 P3.15/CLKOUT P4.0/A16 P4.1/A17 P4.2/A18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 VSS VDD P1H.1/A9 P1H.0/A8 P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9 P0H.0/AD8 ST10F163 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P4.3/A19 VSS VDD P4.4/A20/SSPCE1 P4.5/A21/SSPCE0 P4.6/A22/SSPDAT P4.7/A23/SSPCLK RD WR/WRL READY ALE EA VDD VSS VPP P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 VDD VSS 5/58 ST10F163 Table 1 : Pin definitions and functions Symbol P5.10 - P5.15 Pin Number( TQFP) 98-100 1- 3 98 99 100 1 2 3 XTAL1 XTAL2 5 6 Input (I) Output (O) I I I I I I I I I O Function 6-bit input-only port with Schmitt-Trigger characteristics. Port 5 pins also serve as timer inputs: P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 T6EUD T5EUD T6IN T5IN T4EUD T2EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input GPT2 Timer T5 Ext.Up/Down Ctrl.Input GPT2 Timer T6 Count Input GPT2 Timer T5 Count Input GPT1 Timer T4 Ext.Up/Down Ctrl.Input GPT1 Timer T2 Ext.Up/Down Ctrl.Input XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. P3.0 - P3.13, P3.15 8- 21 22 9 10 11 12 13 14 15 18 19 20 22 I/O I/O O I IO I I I I O I/O O O O 15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The following Port 3 pins have alternate functions: P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.10 P3.11 P3.12 P3.15 T6OUT CAPIN T3OUT T3EUD T4IN T3IN T2IN TxD0 RxD0 BHE WRH CLKOUT GPT2 Timer T6 Toggle Latch Output GPT2 Register CAPREL Capture Input GPT1 Timer T3 Toggle Latch Output GPT1 Timer T3 Ext.Up/Down Ctrl.Input GPT1 Timer T4 Input for Count/Gate/Reload/Capture GPT1 Timer T3 Count/Gate Input GPT1 Timer T2 Input for Count/Gate/Reload/Capture ASC0 Clock/Data Output (Asyn./Syn.) ASC0 Data Input (Asyn.) or I/O (Syn.) Ext. Memory High Byte Enable Signal, Ext. Memory High Byte Write Strobe System Clock Output (=CPU Clock) 6/58 ST10F163 Table 1 : Pin definitions and functions (continued) Symbol P4.0 - P4.7 Pin Number( TQFP) 23-26 29-32 Input (I) Output (O) I/O Function 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. For external bus configuration, Port 4 can be used to output the segment address lines: P4.0 ... P4.3 P4.4 P4.5 P4.6 P4.7 A16 ... A19 A20 SSPCE1 A21 SSPCE0 A22 SSPDAT A23 SSPCLK Least Significant Segment Addr. Line ... Segment Address Line Segment Address Line SSP Chip Enable Line 1 Segment Address Line SSP Chip Enable Line 0 Segment Address Line SSP Data Input/Output Line Most Significant Segment Addr. Line SSP Clock Output Line 23 ... 26 29 30 31 32 RD WR/WRL 33 34 O ... O O O O O O I/O O O O O External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Ready Input. When the READY function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the device to begin instruction execution out of external memory. A high level forces execution out of the internal flash EPROM. Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. READY 35 I ALE EA 36 37 O I PORT0: P0L.0-P0L.7 P0H.0-P0H.7 41-48 51-58 I/O Demultiplexed bus modes Data Path Width: 8-bit D0 - D7 I/O 16-bit D0 - D7 D8 - D15 P0L.0 - P0L.7: P0H.0 - P0H.7: Multiplexed bus modes Data Path Width: P0L.0 - P0L.7: P0H.0 - P0H.7: 8-bit AD0 - AD7 A8 - A15 16-bit AD0 - AD7 AD8 - AD15 7/58 ST10F163 Table 1 : Pin definitions and functions (continued) Symbol PORT1: P1L.0-P1L.7 P1H.0-P1H.7 RSTIN 59-66 67, 68 71-76 79 I Pin Number( TQFP) Input (I) Output (O) I/O Function Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the device. An internal pullup resistor permits power-on reset using only a capacitor connected to V SS. Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10R65 to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The following Port 6 pins have alternate functions: P6.0 ... P6.4 P6.5 P6.6 P6.7 CS0 ... CS4 HOLD HLDA BREQ Chip Select 0 Output ... Chip Select 4 Output External Master Hold Request Input (Master mode: O, Slave mode: I) 88 89 P2.8 -P2.15 90 - 97 I/O O I/O Hold Acknowledge Output Bus Request Output RSTOUT 80 O NMI 81 I P6.0-P6.7 82-89 I/O 82 ... 86 87 O ... O I Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The following Port 2 pins also serve for alternate functions: P2.8 ... P2.15 EX0IN ... EX7IN Fast External Interrupt 0 Input ... Fast External Interrupt 7 Input 90 ... 97 VPP 40 I ... I - Flash programming voltage. This pin accepts the programming voltage for the on-chip flash EPROM. In the ST10F163, bit 4of SYSCON register serves as an enable/disable control for the OWD. Digital Supply Voltage: + 5 V during normal operation and idle mode. > 2.5 V during power down mode Digital Ground. VDD VSS 7, 28, 38, 49, 69, 78 4, 27, 39, 50, 70, 77 - - 8/58 ST10F163 III - FUNCTIONAL DESCRIPTION The architecture of the ST10F163 combines the advantages of both RISC and CISC processors and an advanced peripheral subsystem. The folFigure 3 : Block diagram 32 Internal FLASH Memory 16 Watchdog 16 PEC CPU-Core 16 16 Internal RAM lowing block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure. Interrupt Controller 16 PLL OSC. 16 Port 0 SSP Ext. Bus Controller GPT1 T2 T3 T4 GPT2 T5 ASC (usart) 16 8 Port 4 Port 1 BRG Port 5 T6 BRG Port 3 Port 2 Port 6 8 6 15 8 9/58 ST10F163 IV - MEMORY ORGANIZATION The memory space of the ST10F163 is configured in a Von-Neumann architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. 1 KByte of on-chip RAM is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) General Purpose Registers (GPRs). 1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for other/future members of the ST10 family. In order to meet the needs of system designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller. V - FLASH MEMORY The ST10F163 provides 128KBytes of on-chip, electrically erasable and re-programmable Flash EPROM. The flash memory is organized in 32 bit wide blocks. This allows double word instructions to be fetched in one machine cycle. The flash memory can be used for both code and data storage. The flash memory is organized into four banks of sizes 8K, 24K, 48K and 48Kbytes (table 2). Each of these banks can be erased indepenTable 2 : FLASH memory bank organisation Bank 0 1 2 3 Addresses (Segment 0) 000000h to 001FFFh 002000h to 007FFFh 018000h to 023FFFh 024000h to 02FFFFh Addresses (Segment 1) 010000h to 011FFFh 012000h to 017FFFh 018000h to 023FFFh 024000h to 02FFFFh Size (bytes) 8K 24K 48K 48K dently. This prevents unnecessary erasing of the whole flash memory when only a partial erasing is required (see Table 2). Typical timing characteristics give 80s for word or double word programming and 800 ms for block erasing, at 25mhz system clock. the flash memory has a typical endurance of 1000 erasing/programming cycles. the flash memory can be programmed, either in a programming board, or in the target system. the code to program or erase the flash memory is executed from an external memory or from the on-chip ram, but not from the flash memory itself. as a flexible and cost-saving alternative, the on-chip bootstrap loader may be used to load and start the programming code. the following considerations must be taken into account for programming or erasing `on-line' in the target system: - While operations are in progress, the flash memory can not be accessed as usual, no branch can be made to the flash memory and no data reads can be taken from the flash memory. - If the two first blocks (8KB + 24KB) of the flash memory are mapped to segment 0, no interrupt or hardware trap must occur during programming or erasing, as this would require a `forbidden' branch to the flash memory. A flash memory protection option, when activated, prevents view access to the contents of the ROM and the on-chip RAM, code operation from within the flash memory continues as normal. During the initialization phase, the first two blocks of the flash memory (8KB + 24KB) can be mapped to segment 0 (addresses 00000h to 07FFFh), or to segment 1 (addresses 10000h to 17FFFh). This makes it possible to use external memory for additional system flexibility. 10/58 ST10F163 V.1 - Programming/erasing with ST Embedded Algorithm Kernel In order to secure flash programming and erasing operations, and also to simplify the software development for programming and erasing the Flash, the ST10F163 Flash is programmed or erased by executing a specific sequence of instructions (called `Unlock Sequence') with command and parameters loaded into GPRs. The Unlock Sequence' invokes embedded kernel routines that checks the validity of the parameters provided by the user, and decodes the command (programming or erasing) and executes it. When performing a programming command, the Embedded Algorithm Kernel automatically times the program pulse widths (taking in account the CPU period provided as a parameter by the user) and verifies proper cell programming. Table 3 : Command -parameters definition COMMAND Single word programming Double Word programming Block programming Sector Erasing Read Status Note When performing an erasing command, the Embedded Algorithm Kernel automatically pre-programs the bank to be erased if it is not already programmed. During erase, the Embedded Algorithm Kernel automatically times the erase pulse widths (taking in account the CPU period provided as a parameter by the user) and verifies proper cell erasing. To start a program/erase operation, the user's application must perform an `Unlock Sequence' to trigger the flash ST Embedded Algorithms Kernel (STEAK). Before using STEAK, proper parameters must be assigned through the R0-R4 registers. The R0 register is the command register. The other registers handle the address and data to be programmed or sector to be erased. Table 3 defines the command sequence. A definition of the codes used in Table 3 is given in Table 4. R0 55Ash DD4sh AA5sh EEEEh 7777h R1 AddOff AddOff BegAddOff 5555h nu R2 W DWL EndAddOff Bnk nu R3 nu DWH SourceAddr Bnk nu R4 2TCL 2TCL 2TCL 2TCL 2TCL The read status for registers R1 to R3 is not used except for the return values, refer to "Return values" on page 13 Table 4 : Code definition Abbreviation s AddOff W DWL,DWH BegAddOff EndAddOff Definition Segment of the target flash memory cell Segment Offset of the target flash memory cell which must be even an value (word-aligned address). Data (word) to be written in flash. Data (double word, DHL = low word, DWH = high word to be written in Flash, Segment Offset of the FIRST target flash memory word to be written in a multiple programming command. This value must be even (word-aligned address) Segment Offset of the LAST Target Flash Memory word to be written in a Multiple programming command. Must be even value (word-aligned address). The value D = (EndAddOff - BegAddOff) must be: 0 <= D < 16384 (ie. up to one page (16 KBytes) can be written in the flash with one multi-word programming command). Start address for the source data (block) to be programmed. This address uses implicitly the data paging mechanism of the CPU. SourceAdd value must respect the rules: - SourceAdd + (EndAddOff - BegAddOff) < 16384. SourceAdd - Page 0 and 1 can NOT be used for source data if SYSCON bit ROMS1 = `1' Bnk 2TCL Note: source data can be located in flash (In pages 0, 1, 6, 7, 8, 9, 10 or 11 if bit ROMS1 = `0', or in pages 4, 5, 6, 7, 8, 9, 10 or 11 if bit ROMS1 = `1'. Number of the Bank to be erased. Note that for security, R2 and R3 must hold the same value. CPU clock period in nseconds (e.g. R4 = 40d means CPU frequency is 25MHz). 11/58 ST10F163 The Flash Unlock Sequence consists of two consecutive writes: the direct addressing mode and the indirect addressing mode. The FCR must represent an even address in the active address space of the flash memory. Rwn can be any unused word GPR (R6 to R15), loaded with a value that results in the same even address as for FCR EXTS MOV MOV #1, #2 FCR, R7 [R7], R7 ; assumes flash is mapped in seg 1 ; first part ; second part For easier coding, the standard data paging addressing scheme is overridden for the two MOV instruction of the Flash Trigger Sequence (EXTS instruction). This also locked both standard and PEC interrupts and class A hardware traps. Must be replace by ATOMIC instruction if standard DPP addressing scheme must be preserved. When the embedded programming/erasing algorithm returns to trigger point, information can be collected through register R0 so the user can take specific actions. Table 5 lists all of the error codes that can be returned in R0. Table 5 : Error code definition ERROR CODE 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah FFh Note MEANING Operation was successful ROMEN bit inside SYSCON is not set Vpp voltage not present Programming operation failed Address value (R1) incorrect: not in Flash address area or odd CPU period out of range (must be between 10 ns to 1000 ns) Not enough free space on system stack for proper operation Incorrect bank number (R2,R3) specified Erase operation failed Bad source address for multi-word programming command Bad number of words to be copied in multi-word programming command: one destination will be out of flash, or one source operand will be out of the source page Unknown or bad command The Flash Embedded Presto Algorithms require at least 45 words on the Internal System Stack for proper operation. The program verifies itself that there is enough free space on the System Stack before performing a programming or erasing operation (by comparing SP value with STKOV+90d). 12/58 ST10F163 V.1.1 - Return values After a single or double word programming command, R0 contains error code, R1 remains unchanged, R2 will contain the data in Flash for location Segment+Segment Offset (R0.[3:0] with R1), R3 will contain the data in Flash for location Segment+Segment Offset +2 (R0[3:0] with R1+2), R4 to R15 remain unchanged. After a multi-word programming command, R0 contains error code, R1 will contains the last segment offset address of the last written word in flash (failing flash address if R0 is not equal to V.1.2 - Programming examples Programming a double word: ; code hereafter assumes that flash is mapped in segment 1 ; i.e. bit ROMS1 = `1' in SYSCON register ; Flash must also be enabled, i.e. bit ROMEN = `1' in SYSCON. MOV R0, #PROGDW ; DD4xh: Double word programming command OR R0, #01h ; Selects segment 1 in flash memory MOV R1, #00224h ; Address to be programmed is 01'0224h MOV R2, #03456h ; Data to be programmed at 01'0224h MOV R3, #04567h ; Data to be programmed at 01'0226h MOV R4, #050d ; 50ns is 20 MHz CPU clock frequency MOV R7, #08000h ; R7 used for Flash trigger sequence #define FCR 08000h ; Flash Unlock Sequence: consists in two consecutive writes, with the direct addressing mode and then the indirect addressing mode. FCR must represent an even address in the active address space of the Flash memory, and Rwn can be any unused word GPR (R6 to R15)loaded with a value resulting in the same even address than FCR EXTS #1, #2 ; flash can be mapped in segment 0 or 1 MOV FCR, R7 ; first part MOV [R7], R7 ; second part NOP ; WARNING: place 2 NOP operations after NOP ; the Unlock sequence to avoid all possible ; pipeline conflict in STEAK programs Note For easier coding, the standard data paging addressing scheme is overrides for the two MOV instruction of the Flash Trigger Sequence (EXTS instruction).This also locked both standard and PEC interrupts and class A hardware traps. Must be replace by ATOMIC instruction if standard DPP addressing scheme must be preserved. zero), R2 and R3 are undefined, R4 to R15 remain unchanged. After erasing command, only R4 to R15 remain unchanged, R0 will contain error code, R1 to R3 are undefined. After status read command, R0 contains error code, R1 contains flash embedded revision, R2 and R3 contains circuit identifiers (R2 = #0787h and R3 = #0101h for this device), R4 to R15 remain unchanged. Programming a block of data: Address 01'9000h to 01'9FFEh (inclusive) is to be programmed. Source data (data to be copied into flash) is located in external RAM from address 03'1000h (to 03'1FFEh, implicitly): ; code hereafter assumes that flash is mapped in segment 1 ; i.e. bit ROMS1 = `1' in SYSCON register ; Flash must also be enabled, i.e. bit ROMEN = `1' in SYSCON. MOV R0, #PROGMW ; AA5xh: Multi word programming command OR R0, #01h ; Selects segment 1 in flash memory 13/58 ST10F163 MOV MOV MOV SCXT R1, #09000h R2, #09FFEh R3, #01000h DPP2,#0Ch ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; First Flash Segment Offset Address Last Flash Segment Offset Address Source data address: use DPP2 as data page pointer Source is in page 12 (0Ch): save previous DPP2 value and load it with source page number 50ns is 20 MHz CPU clock frequency R7 used for Flash trigger sequence flash can be mapped in segment 0 or 1 first part second part WARNING: place 2 NOP operations after the Unlock sequence to avoid all possible pipeline conflict in STEAK programs restore DPP2 - Instructions that configure the internal memory must only be executed from external memory or from the internal RAM. - Whenever the internal memory is disabled, enabled or re-mapped, the DPPs must be explicitly (re)loaded to enable correct data accesses to the internal memory and/or external memory. V.3 - Flash protection The flash protection mode, prevents the reading of data operands in the flash memory by anything but a program executed from the flash memory itself. Flash protection mode permits program branches from, or into the flash memory, but does not permit erasing and programming of the flash memory. Flash protection is controlled by the Protection UPROM Programming Bit (UPROG). UPROG is a 'hidden' one-time programmable bit. It is only accessible in a special mode, entered, for example, via a flash EPROM programming board. If UPROG is set to `1', flash protection is active after reset. By default flash protection is disabled (UPROG=0). For deactivation of flash protection, where the flash memory has to be reprogrammed with updated program/variables, a zero value must be written at every even address in the active address space of the flash memory. This write can only be done by an instruction executed from the internal flash memory itself, e.g. MOV FLASH,ZEROS. MOV R4, #050d MOV R7, #08000h #define FCR 08000h EXTS #1, #2 MOV FCR, R7 MOV [R7], R7 NOP NOP POP DPP2 V.2 - Flash memory configuration The default memory configuration is determined by the state of the EA pin at reset. This value is stored in the Internal ROM enable bit: ROMEN of the SYSCON Register. When ROMEN=0, the internal ROM is disabled and external ROM is used for start-up control. The first 32KBytes of the flash memory area must be re-mapped to segment 1, to enable their later use. This is done by setting the ROMS1 bit of SYSCON to 0. This is done by the externally supplied program, before the execution of the EINIT instruction. If program execution starts from external memory, but access to the flash memory (re-mapped to Bank 1) is required later, one of the following values has to be written to the SYSCON register, before the end of initialization: - If flash is to be mapped to segment 1: xxx100xxxxxxxxxxb (ROMS1=1,SGTDIS=0) - If flash is to be mapped to segment 0: xxx000xxxxxxxxxxb (ROMS1=0,SGTDIS=0) All other parts of the flash memory (addresses 18000h - 1FFFFh) remain unaffected. The SGTDIS Segmentation Disable/Enable must be set to 0 so that the 64KBytes of on-chip memory can be used in addition to the external boot memory. The correct procedure for changing the segmentation registers must be observed, to prevent unwanted trap conditions: 14/58 ST10F163 VI - EXTERNAL BUS CONTROLLER All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes: - 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed - 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed - 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed - 16-/18-/20-/24-bit Addresses, multiplexed 8-bit Data, Deglue logic. Access to very slow memories is supported via a particular `Ready' function. A HOLD/HLDA protocol is available for bus arbitration so that external resources can be shared with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register SYSCON. After setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to'1' the Slave Mode is selected where pin HLDA is switched to input. This allows to directly connect the slave controller to another master controller without glue logic. For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. If an address space of 16 MBytes is used, it outputs all 8 address lines. Note When the on-chip SSP Module is to be used the segment address output on Port 4 must be limi ted to 4 bits (i.e. A19...A16) in order to enable the alternate function of the SSP interface pins. In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable. This gives the choice of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx). This gives access to different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external VI.1 - Programmable chip select timing control The position of the CSx lines can be changed by setting the CSCFG bit in the SYSCON register. By default the CSx lines change half a CPU clock cycle after the rising edge of ALE (20ns @ fCPU = 25 MHz). With the CSCFG bit set (section Figure VII -), the CSx lines change with the rising edge of ALE. In this case, the CSx lines and address lines change at the same time. 15/58 ST10F163 Figure 4 : Chip select delay Normal Demultiplexed Segment (P4) Address (P1) Bus Cycle ALE Lengthen Demultiplexed Bus Cycle ALE Normal CSx Unlatched CSx BUS (P0) RD Data Data BUS (P0) WR Data Data Read/Write Delay Read/Write Delay 16/58 ST10F163 VII - CENTRAL PROCESSING UNIT (CPU) Figure 5 : CPU block diagram CPU SP STKOV STKUN MDH MLD Mul./Div.-HW Bit-Mask Gen. General ALU 16-Bit Barrel-Shift Context Ptr ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. Purpose Registers R15 16 128KBytes FLASH ROM 32 Exec. Unit Instr. Ptr Instr. Reg 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs Internal RAM 1KByte R15 R0 16 R0 The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the ST10F163's instructions can be executed in one machine cycle. This requires 80ns at 25MHz CPU clock. For example, shift and rotate instructions are always processed in one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized for speed: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. The `Jump Cache' pipeline optimization, reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. The CPU includes an actual register context. This consists of up to 16 wordwide GPRs physically allocated in the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, one register bank may overlap others. A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes exist. 17/58 ST10F163 VIII - INTERRUPT SYSTEM With an interrupt response time from 200 ns to 480ns (in the case of internal program execution), the ST10F163 reacts quickly to the occurrence of non-deterministic events. The architecture of the ST10F163 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In a standard interrupt service, program execution is suspended and a branch to the interrupt vector table is performed. For a PEC service, just one cycle is `stolen' from the current CPU activity. A PEC service is a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is decremented for each PEC service, except for the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are suited to, for example, the transmission or reception of blocks of data. The ST10F163 has 8 PEC channels, each of which offers fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield, exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs, feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. Table 6 shows all of the possible ST10F163 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Table 6 : List of possible interrupt sources, flags, vector and trap numbers Source of Interrupt or PEC Service Request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error Request Flag CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR T2IR T3IR T4IR T5IR T6IR CRIR S0TIR S0TBIR S0RIR S0EIR Enable Flag CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE T2IE T3IE T4IE T5IE T6IE CRIE S0TIE S0TBIE S0RIE S0EIE Interrupt Vector CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT T2INT T3INT T4INT T5INT T6INT CRINT S0TINT S0TBINT S0RINT S0EINT Vector Location 00'0060h 00'0064h 00'0068h 00'006Ch 00'0070h 00'0074h 00'0078h 00'007Ch 00'0088h 00'008Ch 00'0090h 00'0094h 00'0098h 00'009Ch 00'00A8h 00'011Ch 00'00ACh 00'00B0h Trap Number 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 22h 23h 24h 25h 26h 27h 2Ah 47h 2Bh 2Ch 18/58 ST10F163 Table 6 : List of possible interrupt sources, flags, vector and trap numbers (continued) Source of Interrupt or PEC Service Request SSP Interrupt PLL Unlock / OWD Request Flag XP1IR XP3IR Enable Flag XP1IE XP3IE Interrupt Vector XP1INT XP3INT Vector Location 00'0104h 00'010Ch Trap Number 41h 43h The ST10F163 provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, called`Hardware Traps'. Hardware traps cause an immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an indi- vidual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Table 7 shows all of the possible exceptions or error conditions that can arise during run time. Table 7 : Exceptions or error conditions that can arise during run-time Exception Conditio n Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00'0008h 00'0010h 00'0018h 02h 04h 06h II II II RESET RESET RESET 00'0000h 00'0000h 00'0000h 00h 00h 00h III III III Trap Flag Trap Vector Vector Location Trap Number Trap Priority Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h [2Ch -3Ch] Any [00'0000h- 00'01FCh] in steps of 4h 0Ah 0Ah 0Ah 0Ah 0Ah [0Bh - 0Fh] Any [00h - 7Fh] Current CPU Priority I I I I I Software Traps: TRAP Instruction 19/58 ST10F163 IX - GENERAL PURPOSE TIMER (GPT) UNIT The GPT unit is a flexible multifunctional timer/ counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module. IX.1 - GPT1 Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation: timer, gated timer, and counter mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable pre-scaler. In counter Mode a timer is clocked in reference to external events. Gated timer mode supports pulse width or duty cycle measurement, where the operation of a timer is controlled by the `gate' level on an external input pin. Each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 8 lists the timer input frequencies, resolution and periods for each pre-scaler option at 25 MHz CPU clock (see Table 8). The count direction (up/down) for each timer is programmable by software or is altered dynamically by an external signal on a port pin (TxEUD). For example, this facilitates position tracking. Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow/underflow. The state of this latch may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as reload or capture registers, timers T2 and T4 are stopped. The content of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4, triggered, either by an external signal or by a selectable state transition of its toggle latch, T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. IX.2 - GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. Table 9 lists the timer input frequencies, resolution and periods for each pre-scaler option at 25 MHz CPU clock. Table 8 : GPT1 timer input frequencies, resolution and periods fCPU = 25MHz 000 B Pre-scaler factor Input Frequency Resolution Period 8 3.125MHz 320 ns 21.0 ms 001B 16 1.563MHz 640 ns 41.9 ms Timer Inpu t Selection T2I / T3I / T4I 010B 32 781.3kHz 128 ns 83.9 ms 011B 64 390.6kHz 2.56 s 167 ms 100 B 128 195.3kHz 5.12 s 336 ms 101B 256 97.66kHz 10.24 s 671 ms 110B 512 48.83kHz 20.48 s 1.34 s 111B 1024 24.41kHz 40.96 s 2.68 s 20/58 ST10F163 Table 9 : GPT2 timer input frequencies, resolution and period fCPU = 25MHz 000B Pre-scaler factor Input Frequency Resolution Period 4 6.25MHz 160ns 10.49ms 001B 8 3.125MHz 320 ns 21.0 ms 010B 16 1.563MHz 640 ns 41.9 ms Timer Input Selection T5I / T6I 011B 32 781.3kHz 128 ns 83.9 ms 100B 64 390.6kHz 2.56 s 167 ms 101B 128 195.3kHz 5.12 s 336 ms 110B 256 97.66kHz 10.24 s 671 ms 111 B 512 48.83kHz 20.48 s 1.34 s Figure 6 : Block diagram of GPT1 T2EUD U/D 2 n=3...10 n CPU Clock T2IN T2 Mode Control GPT1 Timer T2 Reload Capture Interrupt Request CPU Clock 2n n=3...10 T3EUD T3IN T3 Mode Control T3OUT GPT1 Timer T3 U/D T3OTL T4IN CPU Clock T4 Mode Control 2n n=3...10 Capture Reload Interrupt Request Interrupt Request GPT1 Timer T4 U/D T4EUD 21/58 ST10F163 Figure 7 : Block diagram of GPT2 T5EUD CPU Clock T5IN U/D 2n n=2...9 T5 Mode Control GPT2 Timer T5 Clear Capture Interrupt Request CAPIN GPT2 CAPREL Reload Toggle FF GPT2 Timer T6 U/D T6EUD Interrupt Request Interrupt Request T6IN CPU Clock 2n n=2...9 T6 Mode Control T60TL T6OUT 22/58 ST10F163 X - PARALLEL PORTS The ST10F163 provides up to 77 I/O lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as, either inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/ O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. All port lines have associated, programmable, alternate input or output functions. PORT0 and PORT1 may be used as address and data lines when accessing external memory. Port 4 outputs the additional segment address bits A23/ 19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for timer control signals. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. ponents is provided by two serial interfaces, an Asynchronous/Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP). ASC0: The table below shows the baud rates for the asynchronous/synchronous serial channel. A dedicated baud rate generator is used to set up all standard baud rates without oscillator tuning. 3 separate interrupt vectors are provided for transmission, reception, and erroneous reception. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities have been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register by the time the reception of a new character is complete. XI - SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral com- Table 10 : Commonly used baud rates by reload value and deviation errors S0BRS = `0', fCPU = 25MHz Baud Rate (Baud) 781250 56000 38400 19200 9600 4800 2400 1200 600 95 Deviation Error 0.0% +7.3% +1.7% +1.7% +0.5% +0.5% +0.2% +0.0% +0.0% +0.4% /-0.4% / -3.1% / -0.8% / -0.8% / -0.1% / -0.1% / -0.1% / -0.1% / 0.4% Reload Value 0000 H 000C H / 000DH 0013 H / 0014H 0027 H / 0028H 0050 H/ 0051H 00A1 H / 00A2H 0144 H / 0145H 028A H / 028BH 0515 H / 0516H 1FFF H / 1FFFH Baud Rate (Baud) 520833 56000 38400 19200 9600 4800 2400 1200 600 75 63 Note S0BRS = `1', fCPU = 25MHz Deviation Error 0.0% +3.3% +4.3% +0.5% +0.5% +0.5% +0.0% +0.0% +0.0% +0.0% +0.9% / -7.0% / -3.1% / -3.1% / -1.4% / -0.5% / -0.5% / -0.2% / -0.1% / 0.0% / 0.9% Reload Value 0000 H 0008H / 0009H 000CH / 000DH 001AH / 001BH 0035H / 0036H 006BH / 006CH 00D8H / 00D9H 01B1H / 01B2H 0363H / 0364H 1B1FH / 1B20H 1FFFH / 1FFFH The deviation errors given in the table above are rounded. Using a baudrate crystal will provide correct baudrates without deviation errors. 23/58 ST10F163 SSP: The Synchronous Serial Port provides high-speed serial communication with external slave devices such as EEPROM. The SSP transmits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to a shift clock which is generated by the SSP. The SSP can start shifting with the LSB or with the MSB and is used to select shifting and latching clock edges as well as the clock polarity. Up to two chip select lines may be activated in order to direct data transfers to one or both of two peripheral devices. Table 11 : Synchronous baud rate and SSPCKS reload values SSPCKS Value 000 001 010 011 100 101 110 111 SSP clock = CPU clock divided by 2 SSP clock = CPU clock divided by 4 SSP clock = CPU clock divided by 8 SSP clock = CPU clock divided by 16 SSP clock = CPU clock divided by 32 SSP clock = CPU clock divided by 64 SSP clock = CPU clock divided by 128 SSP clock = CPU clock divided by 256 Synchronous baud rate 12.5 MBit/s 6.25 MBit/s 3.13 MBit/s 1.56 MBit/s 781 KBit/s 391 KBit/s 195 KBit/s 97.7 KBit/s 24/58 ST10F163 XII - WATCHDOG TIMER The Watchdog Timer is a fail-safe mechanism which the maximum malfunction time of the controller The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. In this way the chip's start-up procedure is always monitored. The software must be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a pre-specified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. The Table 12 shows the watchdog time range which for a 25MHz CPU clock. Some numbers are rounded to 3 significant digits. XIII - OSCILLATOR WATCHDOG (OWD) The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock transitions are missing, the OWD activates the PLL Unlock/OWD interrupt node and supplies the CPU with the PLL clock signal. Under these circumstances the PLL will oscillate with its basic frequency. A low level on pin OWE disables the OWD's interrupt output, so that the clock signal is derived from the oscillator clock. The CPU clock source is only switched back to the oscillator clock after a hardware reset. When the direct-drive, or direct-drive-with- prescaler clock option is selected, an oscillator watchdog is implemented. This provides a fail-safe mechanism in the case of a loss of external clock. After reset, the Oscillator Watchdog is enabled by default. To disable the OWD, the bit OWDDIS (bit 4 of SYSCON register) must be set. When the OWD is enabled, PLL runs on free-running frequency, and increments the Oscillator Watchdog counter. On each transition of XTAL1 pin, the Oscillator Watchdog is cleared. If an external clock failure occurs, then the Oscillator Watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal is switched to the PLL free-running clock signal, and the Oscillator Watchdog Interrupt Request (XP3INT) is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always fed from the oscillator input and the PLL is switched off to decrease power supply current. Table 12 : Watchdog time range for 25MHz CPU clock Reload value in WDTREL FF H 00H Note Prescaler for fCPU 2 (WDTIN = `0') 20.48 s 5.24 ms 128 (WDTIN = `1') 1.31 ms 336 ms For security, rewrite WDTCON each time before the watchdog timer is serviced. 25/58 ST10F163 XIV - INSTRUCTION SET SUMMARY The table below lists the instruction set of the ST10F163. More detailed information such as address modes, instruction operation, parameters for conTable 13 : Instruction Set Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Description Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2 2/4 2/4 2/4 4 4 4 4 4 ditional execution of instructions, opcodes and a detailed description of each instruction can be found in the "ST10 Family Programming Manual" 26/58 ST10F163 Table 13 : Instruction Set (continued) Mnemonic CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2 27/58 ST10F163 XV - SPECIAL FUNCTION REGISTER OVERVIEW The following table lists SFRs in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Registers with on-chip X-peripherals (CAN) are marked with the letter "X" in column physical address. Table 14 : Special Function Register List Name ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 BUSCON0 BUSCON1 BUSCON2 BUSCON3 BUSCON4 CAPREL CC8IC CC9IC CC10IC CC11IC CC12IC CC13IC CC14IC CC15IC CP CRIC CSP DP0L DP0H DP1L DP1H DP2 DP3 DP4 DP6 DPP0 DPP1 DPP2 b b b b b b b b b b b b b b b b b b b b b b Physical Address FE18h FE1Ah FE1Ch FE1Eh FF0Ch FF14h FF16h FF18h FF1Ah FE4Ah FF88h FF8Ah FF8Ch FF8Eh FF90h FF92h FF94h FF96h FE10h FF6Ah FE08h F100h F102h F104h F106h FFC2h FFC6h FFCAh FFCEh FE00h FE02h FE04h E E E E 8-Bit Address 0Ch 0Dh 0Eh 0Fh 86h 8Ah 8Bh 8Ch 8Dh 25h C4h C5h C6h C7h C8h C9h CAh CBh 08h B5h 04h 80h 81h 82h 83h E1h E3h E5h E7h 00h 01h 02h Description Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register EX0IN Interrupt Control Register EX1IN Interrupt Control Register EX2IN Interrupt Control Register EX3IN Interrupt Control Register EX4IN Interrupt Control Register EX5IN Interrupt Control Register EX6IN Interrupt Control Register EX7IN Interrupt Control Register CPU Context Pointer Register GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (read only) P0L Direction Control Register P0h Direction Control Register P1L Direction Control Register P1h Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Register (10 bits) CPU Data Page Pointer 2 Register (10 bits) Reset Value 0000h 0000h 0000h 0000h 0XX0h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h FC00h 0000h 0000h 00h 00h 00h 00h 0000h 0000h 00h 00h 0000h 0001h 0002h An SFR can be specified by its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). 28/58 ST10F163 Table 14 : Special Function Register List (continued) Name DPP3 EXICON IDCHIP IDMANUF IDMEM IDPROG MDC MDH MDL ODP2 ODP3 ODP6 ONES P0L P0H P1L P1H P2 P3 P4 P5 P6 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PSW RP0H S0BG S0CON S0EIC S0RBUF S0RIC b b b b b b b b b b b b b b b b b b b b Physical Address FE06h F1C0h F07Ch F07Eh F07Ah F078h FF0Eh FE0Ch FE0Eh F1C2h F1C6h F1CEh FF1Eh FF00h FF02h FF04h FF06h FFC0h FFC4h FFC8h FFA2h FFCCh FEC0h FEC2h FEC4h FEC6h FEC8h FECAh FECCh FECEh FF10h F108h FEB4h FFB0h FF70h FEB2h FF6Eh E E E E E E E E E 8-Bit Address 03h E0h 3Eh 3Fh 3Dh 3Ch 87h 06h 07h E1h E3h E7h 8Fh 80h 81h 82h 83h E0h E2h E4h D1h E6h 60h 61h 62h 63h 64h 65h 66h 67h 88h 84h 5Ah D8h B8h 59h B7h Description CPU Data Page Pointer 3 Register (10 bits) External Interrupt Control Register Device Identifier Register Manufacturer Identifier Register On-chip Memory Identifier Register Programming Voltage Identifier Register CPU Multiply Divide Control Register CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Constant Value 1's Register (read only) Port 0 Low Register (Lower half of PORT0) Port 0 High Register (Upper half of PORT0) Port 1 Low Register (Lower half of PORT1) Port 1 High Register (Upper half of PORT1) Port 2 Register Port 3 Register Port 4 Register (8 bits) Port 5 Register (read only) Port 6 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register CPU Program Status Word System Start-up Configuration Register (Rd. only) Serial Channel 0 Baud Rate Generator Reload Reg Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register Reset Value 0003h 0000h 0A3Xh1) 0400h 3020h 9A40h 0000h 0000h 0000h 0000h 0000h 00h FFFFh 00h 00h 00h 00h 0000h 0000h 00h XXXXh 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXh 0000h 0000h 0000h XXh 0000h 29/58 ST10F163 Table 14 : Special Function Register List (continued) Name S0TBIC S0TBUF S0TIC SP SSPCON0 SSPCON1 SSPRTB SSPTBH STKOV STKUN SYSCON T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC TFR WDT WDTCON XP1IC XP3IC ZEROS b b b b b b b b b b b b b b b b b Physical Address F19Ch FEB0h FF6Ch FE12h EF00h EF02h EF04h EF06h FE14h FE16h FF12h FE40h FF40h FF60h FE42h FF42h FF62h FE44h FF44h FF64h FE46h FF46h FF66h FE48h FF48h FF68h FFACh FEAEh FFAEh F18Eh F19Eh FF1Ch E E X X X X E 8-Bit Address CEh 58h B6h 09h --------0Ah 0Bh 89h 20h A0h B0h 21h A1h B1h 22h A2h B2h 23h A3h B3h 24h A4h B4h D6h 57h D7h C7h CFh 8Eh Description Serial Channel 0 Transmit Buffer Interrupt Control Reg Serial Channel 0 Transmit Buffer Register (write only) Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSP Control Register 0 SSP Control Register 1 SSP Receive/Transmit Buffer SSP Transmit Buffer High CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register SSP Interrupt Control Register PLL unlock Interrupt Control Register Constant Value 0's Register (read only) Reset Value 0000h 00h 0000h FC00h 0000h 0000h XXXXh XXXXh FA00h FC00h 0xx0h2) 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 000xh3) 0000h 0000h 0000h 1. The value depends on the silicon revision and is given in the errata sheet. 2. The system configuration is selected during reset. 3. Bit WDTR indicates a watchdog timer triggered reset. 30/58 ST10F163 XVI - ELECTRICAL CHARACTERISTICS XVI.1 - Absolute maximum ratings - Ambient temperature under bias (TA): 0 to +70 C - Storage temperature (TST):- 65 to +150 C - Voltage on VDD pins with respect to ground (VSS):- 0.5 to +6.5 V - Voltage on any pin with respect to ground (VSS): -0.5 to V DD +0.5 V - Input current on any pin during overload condition: -10 to +10 mA - Absolute sum of all input currents during overload condition:|100 mA| - Power dissipation:1.5 W Note Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VDD or VIN VDD = 5 V 10% VSS = 0 V Reset activeTA = 0 to +70C Table 15 : DC Characteristics Limit Values Parameter Symbol min. Input low voltage Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN Input high voltage XTAL1 Output low voltage1) (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage1 (all other outputs) Output high voltage 1 (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage 1 2) (all other outputs) Input leakage current (all other) RSTIN pull-up resistor 3) Read/Write inactive current 4) VIL VIH VIH1 VIH2 VOL SR SR SR SR CC - 0.5 0.2 VDD + 0.9 0.7 VDD 0.7 VDD - max. 0.2 VDD - 0.1 VDD + 0.5 VDD + 0.5 VDD + 0.5 0.45 V V V V V - - - - IOL = 2.4 mA Unit Test Condition V OL1 VOH CC CC - 0.9 VDD 2.4 0.9 VDD 2.4 - 50 - 0.45 - V V IOL1 = 1.6 mA IOH = - 500 A IOH = -2.4 mA IOH = - 250 A IOH = - 1.6 mA 0 V < VIN < VDD - VOUT = 2.4 V VOH1 IOZ2 RRST IRWH 5) CC - 1 250 -40 V V A K A CC CC 31/58 ST10F163 Table 15 : DC Characteristics (continued) Limit Values Parameter Read/Write active current 4 ALE inactive current 4 ALE active current 4 Port 6 inactive current 4 Port 6 active current4 PORT0 configuration current 4 Symbol min. IRWL 6) IALEL 5 IALEH 6 IP6H 5 IP6L 6 IP0H 5 IP0L 6 XTAL1 input current Pin capacitance 4 (digital inputs/outputs) Power supply current IIL C IO ICC CC CC -500 40 - - -500 - -100 - - - max. - - 500 -40 - -10 - 20 10 20 + 3.5 * fCPU 10 + 1.2 * fCPU 50 A A A A A A A A pF mA V OUT = VOLmax V OUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max VIN = VIHmin VIN = VILmax 0 V < VIN < VDD f = 1 MHz TA = 25 C RSTIN = V IL2 fCPU in [MHz] 7) mA RSTIN = VIH1 fCPU in [MHz] 8) VDD = 5.5 V9) Unit Test Condition Idle mode supply current IID - Power-down mode supply current IPD - A 1. ST10F163 pins are equipped with Low-Noise output drivers, which significantly improve the device's EMI performance. These Low-Noise drivers deliver their maximum current only until the respective target output level is reached. After that, the output current is reduced. This results in an increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current specified in column "Test Conditions" is delivered in any case. 2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 3. Not 100% tested, guaranteed by design characterization. 4. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. 5. The maximum current may be drawn while the respective signal line remains inactive. 6. The minimum current must be drawn in order to drive the respective signal line active. 7. The power supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and 25 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The chip is configured with a demux 16-bit bus, direct clock drive, 5 chip select lines and 2 segment address lines, EA pin is low during reset. After reset, Port0 is driven with the value `00CCh' that produces infinite execution of NOP instruction with 15 wait-state, R/W delay, memory tristate waitstate, normal ALE. Peripherals are not activated. 8. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and 25 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. 9. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. 32/58 ST10F163 Figure 8 : Supply/idle current as a function of operating frequency I [mA] 100 ICCmax 50 IIDmax 10 5 XVI.4 - AC characteristics XVI.4.1 - Test waveforms Figure 9 : Input/output waveforms 2.4V 0.2V DD+0.9 10 15 20 25 fCPU [MHz] 0.2V DD+0.9 Test Points 0.45V 0.2V DD-0.1 0.2V DD-0.1 AC inputs during testing are driven at 2.4 V for a logic `1' and 0.4 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. Figure 10 : Float waveforms VOH VOH -0.1V Timing Reference Points VOL +0.1V VOL VLoad +0.1V VLoad V Load -0.1V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (I OH/IOL = 20 mA). 33/58 ST10F163 XVI.4.2 - Definition of internal timing The internal operation of the ST10F163 is controlled by the internal CPU clock fCPU . Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see figure below). The CPU clock signal can be generated by different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate fCPU. This influence must be regarded when calculating the timings for the ST10F163. The example for PLL operation shown in the figure above refers to a PLL factor of 4. The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). Figure 11 : Generation mechanisms for the CPU clock Phase locked loop operation fXTAL fCPU TCLTCL Direct Clock Drive fXTAL fCPU TCLTCL Prescaler Operation fXTAL fCPU TCL TCL XVI.4.3 - Clock generation modes The table below associates the combinations of these three bits with the respective clock generation mode. P0.15-13 (P0H.7-5) 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CPU Frequency fCPU = fXTAL * F FXTAL * 4 FXTAL * 3 FXTAL * 2 FXTAL * 5 FXTAL * 1 FXTAL * 1.5 FXTAL / 2 FXTAL * 2.5 External Clock Input Range 1) 2.5 to 6.25 MHz 3.33 to 8.33 MHz 5 to 12.5 MHz 2 to 5 MHz 1 to 25 MHz 6.66 to 16.6 MHz 2 to 50 MHz 4 to 10 MHz Notes Default configuration Direct drive 2) CPU clock via prescaler3) 1. The external clock input range refers to a CPU clock range of 1...25 MHz. 2. The maximum depends on the duty cycle of the external clock signal. 3. The maximum input frequency is 25 MHz when using an external crystal with the internal oscillator; providing that internal serial resistance of the crystal is less than 40 . However, higher frequency can be applied with an external clock source, but in this case, the input clock signal must reach the defined levels VIL and V IH2. 34/58 ST10F163 XVI.4.4 - Prescaler operation When pins P0.15-13 (P0H.7-5) equal '001' during reset, the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fXTAL. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of fXTAL for any TCL. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL is running on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. XVI.4.5 - Direct drive When pins P0.15-13 (P0H.7-5) equal'011' during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated by the following formula: T CL = 1f *DC min XT AL min DC = duty cycle dog. If bit OWDDIS is set, then the PLL is switched off. XVI.4.6 - Oscillator Watchdog (OWD) When the clock option selected is direct drive or direct drive with prescaler, in order to provide a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is implemented as an additional functionality of the PLL circuitry. This oscillator watchdog operates as follows: After a reset, the Oscillator Watchdog is enabled by default. To disable the OWD, the bit OWDDIS (bit 4 of SYSCON register) must be set. When the OWD is enabled, the PLL is running on its free-running frequency, and increment the Oscillator Watchdog counter. On each transition of XTAL1 pin, the Oscillator Watchdog is cleared. If an external clock failure occurs, then the Oscillator Watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the Oscillator Watchdog Interrupt Request (XP3INT) is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always fed from the oscillator input and the PLL is switched off to decrease power supply current. XVI.4.7 - Phase locked loop For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fXTAL * F). With every F'th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula: 2TCL = 1 f Note XTAL The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL * DC max) instead of TCLmin. If bit OWDDIS in the SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watch- 35/58 ST10F163 The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N * TCL the minimum value is computed using the corresponding deviation DN: TCL m in = TCL * ( 1 - lD l 100 ) NOM N D = 4 - 3 15 3 = 3.8% 3TCL min x ( 1 - 3.8 100 ) NOM = TCL x 0.962 NOM ( 57.72nsec@f = 25MHz ) CP U = 3TCL caused by the PLL jitter is negligible (see Figure 12). XVI.4.8 - Memory cycle variables The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Values TCL * D = ( 4 - N 15 ) [ % ] N where N = number of consecutive TCLs and 1 N 40. So for a period of 3 TCLs (N = 3): This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol tA tC tF Figure 12 : Approximated maximum PLL jitter Max.jitter [%] This approximated formula is valid for 1 < N < 40 and 10MHz < fCPU < 25MHz. 4 3 2 1 2 4 8 16 32 N 36/58 ST10F163 XVI.4.9 - External clock drive XTAL1 VDD = 5 V 10% VSS = 0 V fCPU = fXTAL Parameter Symbol min Oscillator period High time Low time Rise time Fall time tOSC t1 t2 t3 t4 SR SR SR SR SR 401) 182) 182) - - max 1000 - - 102) 102) min 20 62) 62) - - max 500 - - 63) 62) TA = 0 to +70 C fCPU = fXTAL / 2 fCPU = fXTAL * N N = 1.5/2,/2.5/3/4/5 min 40 * N 102) 102) - - max 100 * N - - 102) 102) ns ns ns ns ns Unit 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 2. The input clock signal must reach the defined levels VIL and VIH2. Figure 13 : External clock drive XTAL1 t1 t3 t4 VIH2 t2 VIL tOSC 37/58 ST10F163 XVI.4.10 - Multiplexed bus VDD = 5 V 10% VSS = 0 V TA = 0 to +70C CL = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25-MHz CPU clock without waitstates) Table 16 : Multiplexed bus characteristics Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max. CPU Clock 25 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address/Unlatched CS to valid data in t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t22 t23 t25 t27 CC CC CC CC CC CC CC CC CC SR SR SR SR 10 + tA 4 + tA 10 + tA 10 + tA -10 + tA - - 30 + tC 50 + tC - - - - max. - - - - - 6 26 - - 20 + tC 40 + tC 40 + tA + tC 50 +2t A + tC - 26 + tF - - - - Variable CPU Clock 1/2TCL = 1 to 25MHz min. TCL - 10 + tA TCL 16+ tA TCL - 10 + tA TCL - 10 + tA -10 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC - - - - max. - - - - - 6 TCL + 6 - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 14 + tF - - - - Parameter Symbol Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR ALE rising edge after RD, WR Address/Unlatched CS hold after RD, WR SR SR CC CC CC CC 0 - 20 + tC 26 + tF 26 + tF 26 + tF 0 - 2TCL - 20 + tC 2TCL - 14 + tF 2TCL - 14 + tF 2TCL - 14 + tF 38/58 ST10F163 Table 16 : Multiplexed bus characteristics (continued) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 39/58 Max. CPU Clock 25 MHz min. ALE falling edge to Latched CS Latched CS low to Valid Data In t38 t39 t40 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t54 t56 CC SR -4 - tA - max. 10 - tA 40 + tC + 2tA - - - 0 20 16 + tC 36 + tC - - - - 20 + tF - - Variable CPU Clock 1/2TCL = 1 to 25MHz min. -4 - tA - max. 10 - tA 3TCL - 20 + tC + 2tA - - - 0 TCL 2TCL - 24 + tC 3TCL - 24 + tC - - - - 2TCL - 20 + tF - - Parameter Symbol Latched CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS CC CC CC CC CC SR SR CC CC CC SR SR CC CC 46 + tF 16 + tA -4 + tA - - - - 30 + tC 50 + tC 26 + tC 0 - 20 + tF 20 + tF 3TCL - 14 + tF TCL - 4 + tA -4 + t A - - - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL 14+ tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF ST10F163 Figure 14 : External Memory Cycle: multiplexed bus, with/without read/write delay, normal ALE CLKOUT t5 ALE t16 t25 t6 CSx t38 t17 t40 t39 t27 t6 A23-A16 (A15-A8) BHE t17 Address t27 t16 Read Cycle BUS P0 t6m Address t7 t18 Data In Address t8 RD t10 t14 t12 t19 t13 t9 Write Cycle BUS P0 Address t11 t15 Data Out t23 t8 WR, WRL, WRH t22 t12 t13 t9 40/58 ST10F163 Figure 15 : External Memory Cycle: multiplexed bus, with/without read/write delay, extended ALE CLKOUT t5 ALE t16 t25 t6 t38 t17 t39 t27 t40 CSx t6 A23-A16 (A15-A8) BHE Read Cycle t17 Address t27 t6 BUS P0 Address t7 Data In t8 t9 RD t10 t11 t14 t15 t12 t18 t19 Write Cycle BUS P0 Address t13 Data Out t23 t8 t9 WR WRL, WRH t10 t11 t22 t13 t12 41/58 ST10F163 Figure 16 : External Memory Cycle: multiplexed bus, with/without read/write delay, normal ale, read/ write chip select CLKOUT t5 ALE t16 t25 t6 A23-A16 (A15-A8) BHE t17 Address t27 t16 Read Cycle BUS P0 t6 Address t7 t51 Data In Address t42 RdCSx t44 t46 t48 t52 t49 t43 Write Cycle BUS P0 Address t45 t47 Data Out t56 t42 WrCSx t50 t48 t49 t43 42/58 ST10F163 Figure 17 : External Memory Cycle: multiplexed bus, with/without read/write delay, extended ale, read/ write chip select CLKOUT t5 ALE t16 t25 A23-A16 (A15-A8) BHE t6 t17 Address t54 Read Cycle t6 BUS P0 Address t7 Data In t42 t43 RdCSx t44 t45 t46 t48 t47 t49 t18 t19 Write Cycle BUS P0 Address Data Out t42 t43 WR WRL, WRH t44 t45 t50 t56 t48 t49 43/58 ST10F163 XVI.4.11 - Demultiplexed bus VDD = 5 V 10% VSS = 0 V TA = 0 to +70 C CL = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Table 17 : Demultiplexed bus characteristics Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max. CPU Clock = 25MHz min. ALE high time Address setup to ALE Address/Unlatched CS setup to RD, WR (with RW-delay) Address/Unlatched CS setup to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in t5 t6 t80 t81 t12 t13 t14 t15 t16 t17 t18 t20 CC CC CC CC CC CC SR SR SR 10 + tA 4 + tA 30 + 2tA 10 + 2tA 30 + tC 50 + tC - - - max. - - - - - - 20 + tC 40 + tC 40 + tA + tC 50 + 2tA + tC - 26 + tF Variable CPU Clock 1/2TCL = 1 to 25MHz min. TCL 10+ tA TCL 16+ tA 2TCL - 10 + 2t A TCL -10 + 2t A 2TCL - 10 + tC 3TCL - 10 + tC - - - max. - - - - - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2t A + tC - 2TCL - 14 + tF + 2tA1) Parameter Symbol Address/Unlatched CS to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay 1)) SR SR SR - 0 - - 0 - Data float after RD rising edge (no RW-delay1)) t21 SR - 10 + tF - TCL - 10 + tF + 2tA1) Data valid to WR Data hold after WR ALE rising edge after RD, WR Address/Unlatched CS hold after RD, WR 2) ALE falling edge to Latched CS t22 t24 t26 t28 t38 CC CC CC CC CC 20 + tC 10 + tF -10 + tF 0 + tF -4 - t A - - - - 10 - tA 2TCL- 20 + tC TCL 10+ tF -10 + tF 0 + tF -4 - t A - - - - 10 - tA 44/58 ST10F163 Table 17 : Demultiplexed bus characteristics (continued) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 45/58 Max. CPU Clock = 25MHz min. Latched CS low to Valid Data In Latched CS hold after RD, WR t39 t41 t82 t83 t46 t47 t48 t49 t50 t51 t53 t68 t55 t57 SR CC CC CC SR SR CC CC CC SR SR SR CC CC - 6 + tF 26 + 2tA 6 + 2tA - - 30 + tC 50 + tC 26 + tC 0 - - -10 + tF 6 + tF max. 40 + tC+ 2tA - - - 16 + tC 36 + tC - - - - 20 + tF 0 + tF - - Variable CPU Clock 1/2TCL = 1 to 25MHz min. - TCL - 14 + tF 2TCL - 14 + 2t A TCL -14 + 2t A - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14 + tC 0 - - -10 + tF TCL - 14 + tF max. 3TCL - 20 + tC + 2tA - - - 2TCL - 24 + tC 3TCL - 24 + tC - - - - 2TCL - 20 + tF TCL - 20 + tF - - Parameter Symbol Address setup to RdCS, WrCS (with RW-delay) Address setup to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS 1. RW-delay and tA refer to the following bus cycle. 2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles ST10F163 Figure 18 : External Memory Cycle: demultiplexed bus, with/without read/write delay, normal ALE CLKOUT t5 ALE t16 t26 t6 t38 CSx t17 t39 t41 t41u t6 A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 t17 Address t28 t18 Data In t80 t81 t14 t15 t21 t20 RD t12 t13 Write Cycle P0 BUS (D15-D8) D7-D0 Data Out t80 t81 t22 t24 WR(L), WRH t12 t13 46/58 ST10F163 Figure 19 : External Memory Cycle: demultiplexed bus, with/without read/write delay, extended ALE CLKOUT t5 ALE t16 t26 t6 t38 t17 CSx A23-A16 (A15-A8) BHE t41 t39 t28 t6 t17 Address t28 Read Cycle P0 BUS (D15-D8) D7-D0 t18 Data In t80 t81 RD t14 t15 t21 t20 t12 t13 Write Cycle P0 BUS (D15-D8) D7-D0 Data Out t80 t81 t22 t24 WR(L), WRH t12 t13 47/58 ST10F163 Figure 20 : External Memory Cycle: demultiplexed bus, with/without read/write delay, normal ale, read/ write chip select CLKOUT t5 ALE t16 t26 t6 A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 t17 Address t55 t51 Data In t82 t83 t46 t47 t53 t68 RdCsx t48 t49 Write Cycle P0 BUS (D15-D8) D7-D0 Data Out t82 t83 t50 t57 WrCSx t48 t49 48/58 ST10F163 Figure 21 : External Memory Cycle: demultiplexed bus, no read/write delay, extended ale, read/write chip select CLKOUT t5 ALE A23-A16 (A15-A8) BHE t16 t26 t6 t17 Address t55 Read Cycle P0 BUS (D15-D8) D7-D0 t51 Data In t82 t83 RdCSx t46 t47 t68 t53 t48 t49 Write Cycle P0 BUS (D15-D8) D7-D0 Data Out t82 t83 t50 t57 WrCSx t48 t49 49/58 ST10F163 XVI.4.12 - CLKOUT and READY VDD = 5 V 10% VSS = 0 V TA = 0 to +70 C CL = 100 pF Table 18 : CLKOUT and READY characteristics Unit ns ns ns ns ns ns ns ns ns ns ns ns Max. CPU Clock = 25MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60 CC CC CC CC CC CC SR SR SR SR SR SR 40 14 10 - - 0 + tA 14 4 58 14 4 0 max. 40 - - 4 4 10 + tA - - - - - 0 + 2t A + tC + tF 2) Variable CPU Clock 1/2TCL = 1 to 25MHz min. 2TCL TCL - 6 TCL - 10 - - 0 + tA 14 4 2TCL + 18 14 4 0 max. 2TCL - - 4 4 10 + t A - - - - - TCL - 20 + 2tA + tC + tF 2) Parameter Symbol 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle 50/58 ST10F163 Figure 22 : CLKOUT and READY Running cycle 1) READY waitstate MUX/Tristate 6) CLKOUT t32 t30 t34 t33 t31 t29 ALE 7) Command RD, WR 2) t35 Sync READY t58 Async READY 3) 5) 3) t36 t35 3) t36 t59 t58 3) t59 t604) t37 see 6) 1. Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t 37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). 6. Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7. The next external bus cycle may start here. 51/58 ST10F163 XVI.4.13 - External bus arbitration VDD = 5 V 10% C L (for Port 6, CS) = 100 pF Unit ns ns ns ns ns ns ns Max. CPU Clock = 25MHz min. HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive t61 t62 t63 t64 t65 t66 t67 SR CC CC CC CC CC CC 20 - - - -4 - -4 max. - 20 20 20 24 20 24 Variable CPU Clock 1/2TCL = 1 to 25MHz min. 20 - - - -4 - -4 max. - 20 20 20 24 20 24 VSS = 0 V TA = 0 to +70 C C L (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Parameter Symbol Figure 23 : External bus arbitration, releasing the bus CLKOUT t61 HOLD t63 HLDA 1) t62 BREQ t64 3) 2) CSx (On P6.x) t66 Other Signals 1) 1. The ST10F163 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to get active. 3. The CS outputs will be resistive high (pullup) after t64. 52/58 ST10F163 Figure 24 : External bus arbitration, (regaining the bus) 2) CLKOUT t61 HOLD t62 HLDA t62 BREQ t62 1) t63 t65 CSx (On P6.x) t67 Other Signals 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F163 requesting the bus. 2. The next ST10F163 driven bus cycle may start here. 53/58 ST10F163 XVI.4.14 - Synchronous serial port timing V CC = 5 V 10% VSS = 0 V TA = 0 to +70 C CL = 100 pF Table 19 : Synchronous serial port timing characteristics Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Max. Baudrate = 12.5 / 10 MBd min. SSP clock cycle time SSP clock high time SSP clock low time SSP clock rise time SSP clock fall time CE active before shift edge CE inactive after latch edge Write data valid after shift edge Write data hold after shift edge Write data hold after latch edge Read data active after latch edge Read data setup time before latch edge Read data hold time after latch edge t200 t201 t202 t203 t204 t205 t206 t207 t208 t209 t210 t211 t212 CC CC CC CC CC CC CC CC CC CC SR SR SR 80 / 100 30 / 40 30 / 40 -/- -/- 30 / 40 70 / 90 -/- 0/0 34 / 44 50 / 60 20 / 20 0/0 max. 80 /100 -/- -/- 6/6 6/6 -/- 90 / 110 10 / 10 -/- 46 / 56 -/- -/- -/- Variable Baudrate = 0.5 to 12.5 MBd min. 4 TCL t200/2 - 10 t200/2 - 10 - - t200/2 - 10 t200 - 10 - 0 t200/2 - 6 t200/2 + 10 20 0 max. 512 TCL - - 6 6 - t200 + 10 10 - t200/2 + 6 - - - Parameter Symbol Figure 25 : SSP write timing 1) t200 t202 t201 2) SSPCLK t203 t205 SSPCEx t204 t206 3) t207 SSPDAT 1st Bit t207 2nd Bit t208 t207 t209 Last Bit 54/58 ST10F163 Figure 26 : SSP read timing 2) 1) SSPCLK t206 SSPCEx 3) t210 t209 SSPDAT last Wr. Bit t211 1st.In Bit Lst.In Bit t212 The transition of shift and latch edge of SSPCLK is programmable. This figure uses the falling edge as shift edge (drawn bold). The bit timing is repeated for all bits to be transmitted or received. The active level of the chip enable lines is programmable. This figure uses an active low CE (drawn bold). At the end of a transmission or reception the CE signal is disabled in single transfer mode. In continuous transfer mode it remains active. 55/58 ST10F163 XVII - PACKAGE MECHANICAL DATA Figure 27 : Package outline TQFP100 (14 x 14 mm) A A2 100 e A1 76 0,075 mm 0.03 inch 75 SEATING PLANE 1 25 51 c 26 D3 D1 D 50 L1 L E3 E1 E 0,25 mm .010 inch GAGE PLANE K Millimeters Dimensions Min. A A2 D D1 D3 E E1 E3 e ND NE N 15.75 13.90 1.35 15.75 13.90 1.40 16.00 14.00 12.00 16.00 14.00 12.00 0.50 Number of Pins 25 25 100 16.25 14.10 0.620 0.547 Typ. Max. 1.60 1.45 16.25 14.10 0.053 0.620 0.547 Min. Inches Typ. Max. 0.063 0.055 0.630 0.551 0.472 0.630 0.551 0.472 0.020 0.640 0.555 0.057 0.640 0.555 XVIII - ORDERING INFORMATION Salestype ST10F163BT1 Temperature range 0C to 70C Package TQFP100 (14x 14) 56/58 B ST10F163 XIX - REVISION HISTORY The following changes have been made from ST10F163 Data Sheet revision 5 to create this revision 6: Table added Table added Table added Table added Table added Table added Table added Table added Presentation changed Specification changed Specification changed Specification changed Specification changed Specification changed Specification changed Specification changed Table 8 on page 20 Table 9 on page 21 Table 10 on page 23 Table 11 on page 24 Table 12 on page 25 Table 3 on page 11 Table 4 on page 11 Table 5 on page 12 Figure 14 to Figure 21 t22 from 2TCL-16+t c to 2TCL-20+t c t8 - t9 replaced with t80 - t81 for demultiplexed bus t42 - t43 replaced with t82 - t83 for demultiplexed bus t35 from 10ns to 14ns t36 and t59 from 0ns to 4ns t37 from "min 54ns, Var min 2TCL+14ns" to "min 58ns, Var min 2TCL+18ns" Table 15: input hight voltage RSTIN, min. 0.6V DD chnaged to 0.7VDD 57/58 ST10F163 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http ://www.st.com 58/58 |
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